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integrated device technology, inc. military and commercial temperature ranges august 1995 1995 integrated device technology, inc. 11.7 dsc-9028/7 32-bit flow-thru error detection and correction unit idt49c465 idt49c465a the idt logo is a registered trademark and flow-thruedc is a trademarkof integrated device technology inc. features 32-bit wide flow-thruedc ? unit, cascadable to 64 bits single-chip 64-bit generate mode separate system and memory buses on-chip pipeline latch with external control supports bidirectional and common i/o memories corrects all single-bit errors detects all double-bit errors, some multiple-bit errors error detection time ?12ns error correction time ?14ns on chip diagnostic registers. parity generation and checking on system data bus low power cmos ?100ma typical at 20mh z 144-pin pga and pqfp packages military product compliant to mil-std 883, class b description the idt49c465/a is a 32-bit, two-data bus, flow-thruedc unit. the chip provides single-error correction and two and three bit error detection of both hard and soft memory errors. it can be expanded to 64-bit widths by cascading 2 units, without the need for additional external logic. the flow- thruedc has been optimized for speed and simplicity of control. the edc unit has been designed to be used in either of two configurations in an error correcting memory system. the bidirectional configuration is most appropriate for systems using bidirectional memory buses. a second system configuration utilizes external octal buffers, and is well suited for systems using memory with separate i/o buses. the idt49c465/a supports partial word writes, pipelining and error diagnostics. it also provides parity protection for data on the system side. 2552 drw 01 simplified functional block diagram md latch memory checkbit generator checkbit latch mux byte mux system checkbit generator mux detect logic correct logic expansion logic syndrome generator sd latch pipeline latch md 0?1 mle cbi 0? pcbi 0? sd 0?1 sle ple control control control control cbo 0? merr err 1
11.7 2 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges pin configuration pqfp top view 2552 drw 02 49c465y pq144-2 1 144 109 108 73 72 37 36 v cc md 30 md 29 md 28 md 27 md 26 md 25 md 24 gnd md 23 md 22 md 21 md 20 md 19 md 18 md 17 md 16 gnd moe mle md 15 md 14 md 13 md 12 md 11 md 10 gnd md 9 md 8 md 7 md 6 md 5 md 4 md 3 v cc v cc v cc sd 5 sd 6 sd 7 sd 8 sd 9 sd 10 sd 11 gnd be 1 sd 12 sd 13 sd 14 sd 15 sle ple soe gnd sd 16 sd 17 sd 18 sd 19 be 2 sd 20 sd 21 sd 22 gnd sd 23 sd 24 sd 25 sd 26 sd 27 be 3 sd 28 v cc v cc sd 4 be 0 sd3 sd 2 sd 1 sd 0 pcbi 7 pcbi 6 pcbi 5 pcbi 4 pcbi 3 pcbi 2 pcbi 1 pcbi 0 code id 1 code id 0 gnd gnd mode 1 mode 0 merr err syo 7 syo 6 sy0 5 sy0 4 gnd sy0 3 syo 2 syo 1 syo 0 md 0 md 1 md 2 v cc v cc vcc md 31 cbi 7 cbi 6 cbi 5 cbi 4 gnd cbi 3 cbi 2 cbi 1 cbi 0 clear sclken synclk mode 2 p 0 p 1 gnd gnd p 2 p 3 perr psel cbo 7 cbo 6 cbo 5 cbo 4 cboe cbo 3 cbo 2 cbo 1 cbo 0 sd 31 sd 30 sd 29 v cc
11.7 3 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges pin configuration 2552 drw 03 pga (cavity up) top view abc defghj klmnp r 11 10 9 8 7 6 5 4 3 2 1 15 14 13 12 v cc sd 2 sd 6 sd 4 sd 5 sd 7 sd 10 sd 12 sd 11 sd 9 sd 15 sd 13 sd 19 sd 17 sd 18 sd 20 sd 25 sd 22 sd 21 sd 28 sd 26 sd 23 sd 27 sd 29 sd 14 sd 16 pcbi 6 pcbi 5 pcbi 4 pcbi 7 be 0 sd 3 sd 0 pcbi 3 pcbi 1 v cc sd 8 be 1 gnd sle soe ple gnd be 2 gnd sd 24 be 3 v cc v cc v cc sd 30 sd 31 cb0 1 cb0 3 cb0 2 cb0 5 cb0 0 cboe cb0 4 cb0 7 cb0 6 perr psel gnd p 3 p 2 gnd mode 2 p 1 sclk en syn- clk p 0 gnd cb1 0 cb1 6 cb1 3 cb1 1 cb1 7 cb1 4 cb1 2 clear cb1 5 v cc md 31 md 30 md 29 md 26 md 24 md 22 md 19 md 18 md 16 md 17 md 28 md 25 md 23 md 21 v cc md 27 gnd md 20 gnd md 14 moe mle md 15 md 13 md 12 md 11 md 10 md 7 md 4 md 8 gnd md 9 md 6 md 3 v cc v cc gnd gnd gnd code id 1 code id 0 pcbi 0 sd 1 pcbi 2 mode 1 merr err mode 0 md 1 md 5 md 2 v cc syo 7 syo 6 syo 4 syo 5 syo 2 syo 0 syo 3 md 0 syo 1 g144-2 nc* *tied to vcc internally
11.7 4 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges 2552 drw 04 detailed functional block diagram mux error detect pipe latch sd latch parity gen parity check control logic mux mux mux internal final syndro me syndrome generator mux error data latch diagnostic latches byte mux clear internal synclk md checkbit generator mux check bit latch mux md latch sd checkbit generator sd checkbit generator 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 4 4 4 4 4 2 3 err merr syo 0? ple soe be 0? sd 0?1 sle psel p 0? perr synclk sclken clear mode 0? code id 0,1 pcbi 0? cboe cbo 0? moe md 0?1 cbi 0? mle pcbi 0? be 0? internal synclk /err dashed line = diagnostic path error correct 1 of 4 bytes
11.7 5 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges system configurations the idt49c465 edc unit can be used in various configurations in an edc system. the basic configurations are shown below. figure 1 illustrates a bidirectional configuration, which is most appropriate for systems using bidirectional memory buses. it is the simplest configuration to understand and use. during a correction cycle, the corrected data word can be simultaneously output on both the system bus and memory bus. logically, no other parts are required for the correction function. during partial-word-write operations, the new bytes are internally combined with the corrected old bytes for checkbit generation and writing to memory. figure 1. common i/o configuration figure 2 illustrates a separate i/o configuration. this is appropriate for systems using separate i/o memory buses. this configuration allows separate input and output memory buses to be used. corrected data is output on the sd outputs for the system and for re-write to memory. partial word-write bytes are combined externally for writing and checkbit generation. figure 3 illustrates a third configuration which utilizes external buffers and is also well suited for systems using memory with separate i/o buses. since data from memory does not need to pass through the part on every cycle, the edc system may operate in ?us-watch?mode. as in the separate i/o configuration, corrected data is output on the sd outputs. figure 4 illustrates the single-chip generate-only mode for very fast 64-bit checkbit generation in systems that use separate checkbit-generate and detect-correct units. if this is not desired, 64-bit checkbit generation and correction can be done with just 2 edc units. 64-bit correction is also straight- forward, fast and requires no extra hardware for the expansion. figure 2. separate i/o configuration figure 3. bypassed separate i/o configuration figure 4. separate generate/correction units with 64-bit checkbit generation buffer memory output bus memory input bus memory input bus check bits out check bits in cbo 64-bit gen. only edc buffer buffer buffer cbi lower data upper data edc edc cpu bus 2552 drw 08 cpu i/o memory i/o checkbits sd md cbi cbo edc 2552 drw 05 ext.buffer memory input bus checkbit i/o memory output bus ext. buffer ext. buffer cpu bus edc sd md cbi cbo 2552 drw 07 cpu memory inputs memory outputs checkbits cbo cbi md sd edc ext. buffer 2552 drw 06
11.7 6 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges functional description the error detection/correction codes consist of a modified hamming code; it is identical to that used in the idt49c460. 32-bit mode (code id 1,0=00) figure 5. 32-bit mode v cc checkbits?n checkbits?ut syndrome?ut cbo syo pcbi cbi 0? cbi 7 edc 7 7 7 8 2552 drw 09 64-bit mode (code id 1,0=10 & 11) the expansion bus topology is shown in figure 6. this topology allows the syndrome bits used by the correction logic to be generated simultaneously in both parts used in the expansion. during a 64-bit detection or correction operation, ?artial-checkbit?data and ?artial-syndrome?data is simul- taneously exchanged between the two edc units in opposite directions on dedicated expansion buses. this results in very short 64-bit detection and correction times. 8 8 8 8 8 final checkbits?ut (detect and correct) cbo syo err pcbi cbi upper edc partial?heckbits?ut (10) (generate only) partial?yndrome (detect/correct only) partial?heckbits?ut (10) (generate only) partial?heckbits?ut (11) (correction only) cbo syo pcbi cbi checkbits?n lower edc (code id 1,0 = 10) (code id 1,0 = 11) 2552 drw 10 figure 6. 64-bit mode ?2 cascaded idt49c465 devices 64-bit generate-only mode (code id 1,0=01) if the identity pins code id 1,0 = 01, a single edc is placed in the 64-bit ?enerate-only?mode. in this mode, the lower 32 bits of the 64-bit data word enter the device on the md 0-31 inputs and the upper 32-bits of the 64 bit data word enter the figure 7. 64-bit "generate-only" mode (single chip) device on the sd 0-31 inputs. this provides the device with the full 64-bit word from memory. the resultant generated checkbits are output on the cbo 0-7 outputs. the generate time is less than that resulting from using a 2-chip cascade. cbo md 0?1 sd 0?1 edc checkbits?ut lower 32 bits (0?1) upper 32 bits (32?3) 32 32 8 2552 drw 11
11.7 7 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges pin descriptions symbol i/o name and function i/o buses and controls sd 0-7 i/o system data bus : data from md 0-31 appears at these pins corrected if mode 2-0 = x11, or uncor- sd 8-15 rected in the other modes. the be n inputs must be high and the soe pin must be low to enable the sd sd 16-23 output buffers during a read cycle. (also, see diagnostic section.) sd 24-31 separate i/o memory systems: in a write or partial-write cycle, the byte not-to-be-modified is output on sd n to n+7 for re-writing to memory, if be n is high and soe is low. the new bytes to be written to memory are input on the sd n pins, for writing checkbits to memory, if be n is low. bi-directional memory systems: in a write or partial-write cycle, the byte not-to-be-modified is re-directed to the md i/o pins, if be n is high, for checkbit generation and rewriting to memory via the md i/o pins. soe must be high to avoid enabling the output drivers to the system bus in this mode. the new bytes to be written are input on the sd n pins for checkbit generation and writing to memory. be n must be low to direct input data from the system data bus to the md i/o pins for checkbit generation and writing to the checkbit memory. sle i system latch enable : sle is an input used to latch data at the sd inputs. the latch is transparent when sle is high; the data is latched when sle is low. ple i pipeline latch enable : ple is an input which controls a pipeline latch, which controls data to be output on the sd bus and the md bus during byte merges. use of this latch is optional. the latch is transparent when ple is low; the data is latched when ple is high. soe i system output enable : when low, enables system output drivers and parity output drivers if correspond- ing byte enable inputs are high. be 0-3 i byte enables : in systems using separate i/o memory buses, be n is used to enable the sd and parity outputs for byte n. the be n pins also control the byte mux. when be n is high, the corrected or uncorrected data from the memory data latch is directed to the md i/o pins and used for checkbit generation for byte n. this is used in partial-word-write operations or during correction cycles. when be n is low, the data from the system data latch is directed to the md i/o pins and used for checkbit generation for byte n. be 0 controls sd 0-7 be 2 controls sd 16-23 be 1 controls sd 8-15 be 3 controls sd 24-31 md 0-31 i/o memory data bus: these i/o pins accept a 32-bit data word from main memory for error detection and/ or correction. they also output corrected old data or new data to be written to main memory when the edc unit is used in a bi-directional configuration. mle i memory latch enable : mle is used to latch data from the md inputs and checkbits from the cbi inputs. the latch is transparent when mle is high; data is latched when mle is low. when identified as the upper slice in a 64-bit cascade, the checkbit latch is bypassed. moe i memory output enable : moe enables memory data bus output drivers when low. p 0-3 i/o parity i/o : the parity i/o pins for bytes 0 to 3. these pins output the parity of their respective bytes when that byte is being output on the sd bus. these pins also serve as parity inputs and are used in generating the parity error ( perr ) signal under certain conditions (see byte enable definition). the parity is odd or even depending on the state of the parity select pin (psel). psel i parity select : if the parity select pin is low, the parity is even. if the parity select pin is high, the parity is odd. inputs cbi 0-7 i checkbits-in (00) checkbits-in-1 (10) partial-syndrome-in (11): in a single edc system or in the lower slice of a cascaded edc system, these inputs accept the checkbits from the checkbit memory. in the upper slice in a cascaded edc system, these inputs accept the partial- syndrome from the lower slice (detect/correct path). pcbi 0-7 i partial-checkbits-in (10) partial-checkbits-in (11): in a single edc system, these inputs are unused but should not be allowed to float. in a cascaded edc system, the partial-checkbits used by the lower slice are accepted by these inputs (correction path only). in the upper slice of a cascaded edc system, partial-checkbits generated by the lower slice are accepted by these inputs (generate path). code id 1,0 i code identity : inputs which identify the slice position/ functional mode of the idt49c465. (00) single 32-bit edc unit (10) lower slice of a 64-bit cascade (01) 64-bit checkbit-generate-only unit (11) upper slice of a 64-bit cascade 2552 tbl 01
11.7 8 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges pin descriptions (con?.) symbol i/o name and function inputs (con?.) mode 2-0 i mode select: selects one of four operating modes. (x11) normal?mode: normal edc operation (flow-thru correction and generation). (x10) generate-detect?mode: in this mode, error correction is disabled. error generation and detection are normal. (000) error-data-output?mode: allows the uncorrected data captured from an error event by the error-data register to be read by the system for diagnostic purposes. the error-data register is cleared by toggling clear low. the syndrome register and error-data register record the syndrome and uncorrected data from the first error that occurs after they are reset by the clear pin. the syndrome register and error-data register are updated when there is a positive edge on synclk, an error condition is indicated ( err = low), and the error counter indicates zero. all-zero-data source: in error-data-output mode, clearing the error-data register provides a source of all-zero-data for hardware initialization of memory, if this desired. (x01) diagnostic-output mode: in this mode, the contents of the syndrome register , error counter and error- type register are output on the sd bus. this allows the syndrome bytes for an indicated error to be read by the system for error-logging purposes. the syndrome register and the error-data register are updated when there is a positive edge on synclk, an error condition is indicated and the error counter indicates zero errors. thus, the syndrome register saves the syndrome that was present when the first error occurred after the error counter was cleared. the syndrome register and the error counter are cleared by toggling clear low. the error counter lets the system tell if more than one error has occurred since the last time the syndrome register or error-data register was read. (100) checkbit-injection mode: in the checkbit-injection mode, diagnostic checkbits may be input on system data bus bits 0-7 (see diagnostic features - detailed description). clear i clear : when the clear pin is taken low, the error-data register, the syndrome register, the error counter and the error-type register are cleared. synclk i syndrome clock : if err is low, and the error counter indicates zero errors, syndrome bits are clocked into the syndrome register and data from the outputs of the memory data input latch are clocked into the error-data register on the low-to-high edge of synclk. if err is low, the error counter will increment on the low-to-high edge of synclk, unless the error counter indicates fifteen errors. sclken i synclk enable : the sclken enables the synclk signal. synclk is ignored if sclken is high. outputs and enables cbo 0-7 o checkbits-out (00, 01) partial-checkbits-out (10) checkbits-out (11): in a single edc system, the checkbits are output to the checkbit memory on these outputs. in the lower slice in a cascaded edc system, the partial-checkbits used by the upper slice are output by these outputs (generate path only). in the upper slice in a cascade, the final-checkbits appear at these outputs (generate path only). cboe i checkbits out enable : enables checkbit output drivers when low. syo 0-7 o syndrome-out (00) partial-syndrome-out (10) partial-checkbits-out (11): in a 32-bit edc system, the syndrome bits are output on these pins. in the lower slice in a 64-bit cascaded system, the partial-syndrome bits appear at these outputs (detect/ correct path). in the upper slice in a cascaded edc system, the partial-checkbits appear at these outputs (correct path only). in a 64-bit cascaded system, the final-syndrome may be accessed in the diagnostic-output mode from either the lower or the upper slice since the final syndrome is contained in both. err o error : when in normal and detect only modes, a low on this pin indicates that one or more errors have been detected. err is not gated or latched internally. merr o multiple error : when in normal and detect only modes, a low on this pin indicates that two or more errors have been detected. merr is not gated or latched internally. perr o parity error : a low on this pin indicates a parity error which has resulted from the active bytes defined by the 4 byte enable pins. parity error ( perr ) is not gated or latched internally (see byte enable definition). power supply pins vcc 1- 10 p +5 volts gnd 1-12 p ground 2552 tbl 02
11.7 9 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges diagnostic data format (system bus) diagnostic features ?detailed description mode 2-0 x11 ?ormal?mode in this mode, operation is normal or non-diagnostic. x10 ?enerate-detect?mode when the edc unit is in the ?enerate-detect?mode , data is not corrected or altered by the error correction network. (also referred to as the detect-only mode.) 000 ?rror-data-output?mode in this mode, the 32-bit data from the error-data register is output on the sd bus. error data register : the uncorrected data from the memory data bus input latch is stored in the error-data register if the error counter contents indicates 0 and there is a positive transition on the synclk input when the err signal is low. thus, the error-data register contains memory data corresponding to the first error to occur since the register was cleared. this register is cleared by pulling the clear input low. the register is read via the system data bus by entering the ?rror-data-output mode and enabling the system data bus output drivers. all-zero-data : the error-data register can be used as an all-zero-data data source for memory initialization in systems where the initialization process is to be done entirely by hardware. x01 ?iagnostic-output?mode in this mode, data from the diagnostic registers, the pcbi bus and the cbi bus is output on the sd bus. direct checkbit readback : internal data paths allow both the partial-checkbit-input bus and the data in the checkbit- input latch to be read directly by the system bus for diagnostic purposes. both the checkbit input bus and the partial checkbit input bus are read via the system data bus by entering the ?iagnostic-output?mode and enabling the system data bus output drivers. the checkbits are output on system data bus bits 0-7; the partial checkbits are output on bits 8-15. syndrome register: after an error has been detected, the syndrome bits generated are clocked into the internal syndrome register if the error counter contents indicates 0 and there is a positive transition on the synclk input when the err signal is low. this register is cleared by pulling the clear input low. the register is read via the system data bus by entering the ?iagnostic-output?mode and enabling the system data bus outputs. this data is output on sd bits 16-23. error counter : the 4-bit on-board error counter is incremented if the error counter contents do not indicate ff hex, which corresponds to a count of 15, and there is a positive transition on the synclk input when the err signal is low. this counter is cleared by pulling the clear input low. the counter is read via the system data bus by entering the ?iagnostic-output?mode and enabling the system data bus output drivers. this data is output on system data bus bits 24-27. test register : these 2 bits are reserved for factory diagnostics only and must not be used by system software. this data is output on system data bus bits 28-29. error-type register : the error-type register, clocked by the synclk input, saves 2 bits which indicate whether a recorded error was a single or a multiple-bit error. this register holds only the first error type to occur after the last clear operation. this data is output on system data bus bits 30-31. 100 direct read-path checkbit injection : in the ?heckbit-injection?mode , bits 0-7 of the system data input latch are presented to the inputs of the checkbit input latch. if mle is strobed, the checkbit latch will be loaded with this value in place of the checkbits from memory. by inserting various checkbit values, operation of the correction function of the edc can be verified on-board. except for the checkbit-injection function, operation in this mode is identical to normal mode operation. 2552 tbl 03 byte 3 byte 2 byte 1 byte 0 checkbits 0 8 7 16 15 24 23 31 partial checkbits 76543210 s m - - 2 2 2 2 syndrome bits 27 error counter error type re- served latched data data out (unlatched) 7 65432107 6543210 2552 drw 12 30 3 0 1 2
11.7 10 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges operating mode charts slice identification code id 1 code id 0 slice definition 0 0 32-bit flow-thru edc 0 1 64-bit generate only edc 1 0 64-bit edc- lower 32 bits (0-31) 1 1 64-bit edc- upper 32 bits (32-63) 2552 tbl 04 slice position control checkbit buses slice position/ code functional operation pcbi cbi cbo syo p id soe soe sd bus moe moe md bus bus bus bus bus bus perr perr 1 0 width = 32 32 8 8 8 8 4 1 0 0 single 32-bit edc unit generate (1) 1 sys. 0C31 0 sys. byte mux cbs out p in active detect/correct (2) 0 pipe. latch 1 md 0C31 cbs in syn. out p out 0 1 64-bit generate-only 1 sys. 32C63 1 sys. 0C31 cbs out 1 0 lower word, 64-bit bus generate (1) 1 sys. 0C31 0 md 0C31 pcbs out p in active detect/correct (2) 0 pipe. latch 1 md 0C31 u-syoout cbs in par.synd p out 1 1 upper word, 64-bit bus generate (1) 1 sys. 32C63 0 md 32C63 l-cboout f.cbs out p in active detect/correct (2) 0 pipe. latch 1 md 32C63 l-syoout par.cbits p out notes: 2552 tbl 05 1. checkbits generated from the data in the sd latch. 2. corrected data residing in the pipe latch. pcbi cbi cbo syo p functional mode control checkbit buses functional mode of sd bus pcbi cbi cbo syo p mode soe soe sd bus moe moe md bus bus bus bus bus bus perr perr 2 1 0 width = 32 32 8 8 8 8 4 1 x11 ?ormal generate 1 cpu data 0 pipe. latch cb out p in active correct 0 pipe. latch 1 ram data cb in p out x10 ?enerate-detect generate 1 cpu data 0 pipe. latch cb out p in active detect 0 pipe. latch 1 ram data cb in p out 000 ?rror-data-output 0 err. d. latch x01 ?iagnostic-output 0 cbin latch pcbi in cb in pcbiin bus syn. register err. counter er. type reg. 100 ?heckbit-injection generate 1 sdin latch 0 pipe. latch cb out p in active inject checkbits 1 sd0C7 in 0 pipe. latch correct 0 pipe. latch 1 ram data cb in p out 2552 tbl 06
11.7 11 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges primary data path vs. memory configuration cpu buffer sd md p cbo cbi idt49c465 d in d out main memory checkbit memory cpu sd md p cbo cbi idt49c465 i/o main memory checkbit memory 1. checkbit generation write new word to memory 1. checkbit generation write new word to memory cpu buffer sd md p cbo cbi idt49c465 d in d out main memory checkbit memory cpu sd md p cbo cbi idt49c465 i/o main memory checkbit memory 2. data correction read memory word 2. data correction read memory word cpu buffer sd md p cbo cbi idt49c465 d in d out main memory checkbit memory cpu sd md p cbo cbi idt49c465 i/o main memory checkbit memory 3. memory generation re-write corrected word to memory 3. memory generation re-write corrected word to memory corrected corrected corrected corrected corrected separate i/o memories: common i/o memories: 2552 drw 13
11.7 12 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges in order to perform a partial-word-write operation, the complete word in question must be read from memory. this must be done in order to correct any error which may have occurred in the old word. once the complete, corrected word is available, with all the bytes verified, the new word may be assembled in the byte mux and the new checkbits generated. partial-word-write operations for common i/o memories: the example shown above illustrates the case of combin- ing 3 bytes from an old word with a new lower order byte to form a new word. the new word, along with the new checkbits, may now be written to memory. in the separate i/o memory configuration, the situation is similar except that the new word is output on the sd bus instead of the md bus (refer to previous page). 2552 drw 14 b 3 = 1 b 2 = 1 b 1 = 1 b 0 = 0 correction block md latch sd latch pipe latch sd bus byte 3 byte 2 byte 1 byte 0 byte 3 byte 2 byte 1 byte 0 md bus main memory checkbit memory checkbit generator cbo cbi byte mux a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 8 8 8 8 idt49c465
11.7 13 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges 32-bit data word configuration a single idt49c465 edc unit, connected as shown below, provides all the logic needed for single-bit error correction, and double-bit error detection, of a 32-bit data field. the identification code (00) indicates 7 checkbits are required. the cbi 7 pin should be tied high. the 39-bit data format for four bytes of data and 7 checkbits is indicated below. syndrome bits are generated by an exclusive-or of the generated checkbits with the checkbits read from memory. for example, sn is the xor of checkbits from those read with those generated. during data correction, the syndrome bits are used to complement (correct) single-bit errors in the data bits. 32-bit data format 32-bit hardware configuration byte 3 byte 2 byte 1 byte 0 data checkbits c0 c1 c2 c3 c4 c5 c6 0 8 7 16 15 24 23 31 2552 drw 15 pcbi 0C7 cbi 7 cbi 0C6 cbo 0C6 syo 0C6 err merr md 0C31 p 0C3 sd 0C31 syndromeCout memory data i/o checkbitsCout checkbitsCin system data i/o code id 1,0 = 00 v cc 7 8 32 32 7 7 idt49c465 2552 drw 16
11.7 14 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges 64-bit data word configuration two idt49c465 edc units, connected as shown below, provide all the logic needed for single-bit error correction, and double-bit error detection, of a 64-bit data field. the slice identification table gives the code id1,0 values needed for distinguishing the upper 32 bits from the lower 32 bits. final generated checkbits, err and merr (indicates multiple errors) signals come from the upper slice, the ic with code id1,0=11. control signals not shown are connected to both units in parallel. data-in bits 0 through 31 are connected to the same numbered inputs of the edc with code id1,0=10, while data-in bits 32 through 63 are connected to data inputs 0 to 31, respectively, for the edc unit with code id1,0=11. the 72-bit data format of data and checkbits is indicated below. correction of single-bit errors in the 64-bit configuration requires a simultaneous exchange of partial checkbits and partial syndrome bits between the upper and lower units. syndrome bits are generated by an exclusive-or of the generated checkbits with the checkbits read from memory. for example, sn is the xor of checkbits read and checkbits generated. during data correction, the syndrome bits are used to complement (correct) single-bit errors in the data bits. for double or multiple-bit error detection, the data available as output by the pipeline latch is not defined. critical ac performance data is provided in the table key ac calculations, which illustrates the delays that are critical to 64-bit cascaded performance. as indicated, a summation of propagation delays is required when cascading these units. 64-bit data format 64-bit hardware configuration byte 2 byte 1 byte 0 data checkbits c0 c1 c2 c3 c4 c5 c6 0 8 7 16 15 24 23 c7 byte 4 byte 5 byte 6 byte 7 32 31 48 47 40 39 56 55 63 byte 3 2552 drw 17 pcbi 0C7 partialCcheckbits (generate only) cbi 0C7 p 0C3 sd 0C31 syo 0C7 cbo 0C7 idt49c465 lower edc (code id 1,0 = 10) pcbi 0C7 cbi 0C7 p 0C3 sd 0C31 md 0C31 syo 0C7 cbo 0C7 idt49c465 upper edc (code id 1,0 = 11) checkbitsCin system data 0C31 system data 32C63 partialCsyndrome (detect/correct) partialCcheckbits (correct only) final checkbits (generate only) (detect and correct) memory data 32C63 memory data 0C31 8 8 8 8 8 err merr 2552 drw 18
11.7 15 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges definitions of terms: d 0 C d 31 = system data and/or memory data inputs cbi 0 C cbi 7 = checkbit inputs pcbi 0 C pcbi 7 = partial checkbit inputs fs 0 C fs 7 = final internal syndrome bits functional equations: the equations below describe the terms used in the idt49c465 to determine the values of the partial checkbits, checkbits, partial syndromes and final internal syndromes. note: all ? symbols below represent the exclusive- or function. pa = d 0 ? d 1 ? d 2 ? d 4 ? d 6 ? d 8 ? d 10 ? d 12 ? d 16 ? d 17 ? d 18 ? d 20 ? d 22 ? d 24 ? d 26 ? d 28 pb = d 0 ? d 3 ? d 4 ? d 7 ? d 9 ? d 10 ? d 13 ? d 15 ? d 16 ? d 19 ? d 20 ? d 23 ? d 25 ? d 26 ? d 29 ? d 31 pc = d 0 ? d 1 ? d 5 ? d 6 ? d 7 ? d 11 ? d 12 ? d 13 ? d 16 ? d 17 ? d 21 ? d 22 ? d 23 ? d 27 ? d 28 ? d 29 pd = d 2 ? d 3 ? d 4 ? d 5 ? d 6 ? d 7 ? d 14 ? d 15 ? d 18 ? d 19 ? d 20 ? d 21 ? d 22 ? d 23 ? d 30 ? d 31 pe = d 8 ? d 9 ? d 10 ? d 11 ? d 12 ? d 13 ? d 14 ? d 15 ? d 24 ? d 25 ? d 26 ? d 27 ? d 28 ? d 29 ? d 30 ? d 31 pf = d 0 ? d 1 ? d 2 ? d 3 ? d 4 ? d 5 ? d 6 ? d 7 ? d 24 ? d 25 ? d 26 ? d 27 ? d 28 ? d 29 ? d 30 ? d 31 pg = d 8 ? d 9 ? d 10 ? d 11 ? d 12 ? d 13 ? d 14 ? d 15 ? d 16 ? d 17 ? d 18 ? d 19 ? d 20 ? d 21 ? d 22 ? d 23 ph 0 = d 0 ? d 4 ? d 6 ? d 7 ? d 8 ? d 9 ? d 11 ? d 14 ? d 17 ? d 18 ? d 19 ? d 21 ? d 26 ? d 28 ? d 29 ? d 31 ph 1 = d 1 ? d 2 ? d 3 ? d 5 ? d 8 ? d 9 ? d 11 ? d 14 ? d 17 ? d 18 ? d 19 ? d 21 ? d 24 ? d 25 ? d 27 ? d 30 ph 2 = d 0 ? d 4 ? d 6 ? d 7 ? d 10 ? d 12 ? d 13 ? d 15 ? d 16 ? d 20 ? d 22 ? d 23 ? d 26 ? d 28 ? d 29 ? d 31 cmos testing considerations special test board considerations must be taken into account when applying high-speed cmos products to the automatic test environment. large output currents are being switched in very short periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. the techniques listed below will assist the user in obtaining accurate testing results: 1) all input pins should be connected to a voltage potential during testing. if left floating, the device may oscillate, causing improper device operation and possible latchup. 2) placement and value of decoupling capacitors is critical. each physical set-up has different electrical characteristics and it is recommended that various decoupling capacitor sizes be experimented with. capacitors should be positioned using the minimum lead lengths. they should also be distributed to decouple power supply lines and be placed as close as possible to the dut power pins. 3) device grounding is extremely critical for proper device testing. the use of multi-layer performance boards with radial decoupling between power and ground planes is necessary. the ground plane must be sustained from the performance board to the dut interface board and wiring unused interconnect pins to the ground plane is recom- mended. heavy gauge stranded wire should be used for power wiring, with twisted pairs being recommended for minimized inductance. 4) to guarantee data sheet compliance, the input thresholds should be tested per input pin in a static environment. to allow for testing and hardware-induced noise, idt recom- mends using v il 0v and v ih 3 3v for ac tests.
11.7 16 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges detailed description ?checkbit and syndrome generation vs. code id logic equations for the cbo outputs code id 1,0 checkbit 00 10 11 generation final chkbits partial checkbits final checkbits cbo 0 ph 0 ph 1 ph 2 ? pcbi 0 cbo 1 pa pa pa ? pcbi 1 cbo 2 pb pb pb ? pcbi 2 cbo 3 pc pc pc ? pcbi 3 cbo 4 pd pd pd ? pcbi 4 cbo 5 pe pe pe ? pcbi 5 cbo 6 pf pf pf ? pcbi 6 cbo 7 pf pg ? pcbi 7 2552 tbl 07 logic equations for the syo outputs checkbit/ code id 1,0 syndrome 00 10 11 generation final syndrome partial syndrome partial checkbits syo0 ph0 ? cbi0 ph1 ? cbi0 ph2 syo1 pa ? cbi1 pa ? cbi1 pa syo2 pb ? cbi2 pb ? cbi2 pb syo3 pc ? cbi3 pc ? cbi3 pc syo4 pd ? cbi4 pd ? cbi4 pd syo5 pe ? cbi5 pe ? cbi5 pe syo6 pf ? cbi6 pf ? cbi6 pf syo7 pf ? cbi7 pg 2552 tbl 08 32-bit syndrome decode to bit-in-error (1) hex 01234567 s6 00001111 syndrome s5 00110011 bits s4 01010101 hex s3 s2 s1 s0 0 0 0 0 0 * c4 c5 t c6 t t 30 10001 c0tt14tmmt 2 0 0 1 0 c1 t t m t 2 24 t 30011 t188tmttm 4 0 1 0 0 c2t t15t 325t 5 0 1 0 1 t 19 9 t m t t 31 6 0 1 1 0 t 20 10 t m t t m 70111 mttmt426t 8 1 0 0 0 c3 t t m t 5 27 t 9 1 0 0 1 t 21 11 t m t t m a 1 0 1 0 t 22 12 t 1 t t m b 1 0 1 1 17 t t m t 6 28 t c 1 1 0 0 t 23 13 t m t t m d1101 mttmt729t e 1 1 1 0 16t tmtmmt f 1111 tmmt0ttm notes: 2552 tbl 12 1. the table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. the all-zero case indicates no error detected. * = no errors detected # = the number of the single bit-in-error t = two errors detected m = three or more errors detected logic equations for the final syndrome (fsn) final code id 1,0 syndrome 00 10, 11 generation final syndrome final internal syndrome fs 0 ph 0 ? cbi 0 ph 1 (l) ? ph 2 (u) ? cbi 0 fs 1 pa ? cbi 1 pa (l) ? pa (u) ? cbi 1 fs 2 pb ? cbi 2 pb (l) ? pb (u) ? cbi 2 fs 3 pc ? cbi 3 pc (l) ? pc (u) ? cbi 3 fs 4 pd ? cbi 4 pd (l) ? pd (u) ? cbi 4 fs 5 pe ? cbi 5 pe (l) ? pe (u) ? cbi 5 fs 6 pf ? cbi 6 pf (l) ? pf (u) ? cbi 6 fs 7 pf (l) ? pg (u) ? cbi 7 2552 tbl 09
11.7 17 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges detailed description ?32-bit configuration 32-bit modified hamming code ?checkbit encoding chart (1) generated participating data bits checkbits parity 0123456789101112131415 cb0 even (xor) x x xxxx x x cb1 even (xor) x x xxxxxx cb2 odd (xnor) x x x x x x x x cb3 odd (xnor) x x x x x x x x cb4 even (xor) xxxxxx xx cb5 even (xor) x x x xxxxx cb6 even (xor) xxxxxxxx 2552 tbl 10 generated participating data bits checkbits parity 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cb0 even (xor) x x x x x x x x cb1 even (xor) x x xxxxxx cb2 odd (xnor) x x x x x x x x cb3 odd (xnor) x x x x x x x x cb4 even (xor) xxxxxx xx cb5 even (xor) x x x xxxxx cb6 even (xor) x x x xxxxx note: 2552 tbl 11 1. the table indicates the data bits participating in the checkbit generation. for example, checkbit c0 is the exclusive-or function of the 16 data input bits marked with an x.
11.7 18 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges generated participating data bits checkbits parity 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 cb0 even (xor) x x x x x x x x cb1 even (xor) x x x xxxxx cb2 odd (xnor) x x x x x x x x cb3 odd (xnor) x x x x x x x x cb4 even (xor) x x xxxx xx cb5 even (xor) xxxxxxxx cb6 even (xor) xxxxxxxx cb7 even (xor) xxxxxxxx 2552 tbl 15 generated participating data bits checkbits parity 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cb0 even (xor) x x x x x x x x cb1 even (xor) x x x xxxxx cb2 odd (xnor) x x x x x x x x cb3 odd (xnor) x x x x x x x x cb4 even (xor) x x xxxx xx cb5 even (xor) xxxxxxxx cb6 even (xor) xxxxxxxx cb7 even (xor) xxxxxxxx 2552 tbl 14 generated participating data bits checkbits parity 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 cb0 even (xor) x x x x x x x x cb1 even (xor) x x x xxxxx cb2 odd (xnor) x x x x x x x x cb3 odd (xnor) x x x x x x x x cb4 even (xor) x x xxxx xx cb5 even (xor) xxxxxxxx cb6 even (xor) xxxxxxxx cb7 even (xor) xxxxxxxx notes: 2552 tbl 16 1. the table indicates the data bits participating in the checkbit generation. for example, checkbit c0 is the exclusive-or function of the 64 data input bits marked with an x. 2. the checkbit is generated as either an xor or an xnor of the 64 data bits noted by an x in the table. detailed description ?64-bit configuration 64-bit modified hamming code - checkbit encoding chart (1, 2) generated participating data bits checkbits parity 0123456789101112131415 cb0 even (xor) x x x x x x x x cb1 even (xor) x x x xxxxx cb2 odd (xnor) x x x x x x x x cb3 odd (xnor) x x x x x x x x cb4 even (xor) x x xxxx xx cb5 even (xor) xxxxxxxx cb6 even (xor) xxxxxxxx cb7 even (xor) xxxxxxxx 2552 tbl 13
11.7 19 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges detailed description ?64-bit configuration (con?.) 64-bit syndrome decode to bit-in-error (1) hex 0123456789abcdef s7 0000000011111111 s6 0000111100001111 syndrome s5 0011001100110011 bits s4 0101010101010101 hex s3 s2 s1 s0 00000 *c4c5tc6tt62c7tt46tmm 10001 c0tt14tmmttmmtmtt 20010 c1ttmt3456tt5040tmtt 30011 t188tmttmmttmt224 40100 c2tt15t3557tt5141tmtt 50101 t199tmtt63mtt47t325 60110 t2010tmttmmttmt426 70111 mttmt3658tt5242tmtt 81000 c3ttmt3759tt5343tmtt 91001 t2111tmttmmttmt527 a1010 t2212t33ttm49ttmt628 b1011 17ttmt3860tt5444t1tt c1100 t2313tmttmmttmt729 d1101 mttmt3961tt5545tmtt e1110 16ttmtmmttmmt0tt f1111 tmmt32ttm48ttmtmm notes: 2552 tbl 17 1. the table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. the all-zero case indicates no error detected. * = no errors detected # = the number of the single bit-in-error t = two errors detected m = three or more detected t 30 m t 31 t t m m t t m t m m t key ac calculations ?64-bit cascaded configuration 64-bit propagation delay total ac delay for idt49c465 in 64-bit mode (l) = lower slice mode from to (u) = upper slice generate sd bus checkbits out sd to cbo(l) + pcbi to cbo(u) t sc(l) + t pcc(u) detect md bus err for 64-bits md to syo(l) + cbi to err (u) t msy(l) + t ce (u) md bus merr for 64-bits md to syo(l) + cbi to m err t msy(l) + t cme ( u ) correct md bus corrected data out md to syo(l) + cbi to sd(u) t msy(l) + t cs (u) (or) ? md to syo(u) + pcbi to sd(l) t msy(u) + t pcs(l) note: 2552 tbl 18 1. (or) = whichever is worse.
11.7 20 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges capacitance (t a = +25 c, f = 1.0mhz) symbol parameter (1) conditions pkg. typ. unit c in input v in = 0v pga 10 pf capacitance pqfp 5 c out output v out = 0v pga 12 pf capacitance pqfp 7 note: 2552 tbl 20 1. this parameter is sampled and not 100% tested. absolute maximum ratings (1) symbol rating com?. mil. unit v cc power supply C0.5 to +7.0 C0.5 to +7.0 v voltage v term terminal voltage C0.5 to C0.5 to v with respect v cc + 0.5 v cc + 0.5 to ground t a operating 0 to +70 C55 to +125 c temperature t bias temperature C55 to +125 C65 to +135 c under bias t stg storage C55 to +125 C65 to +150 c temperature i out dc output 30 30 ma current note: 2552 tbl 19 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods of time may affect reliability. dc electrical characteristics over operating range the following conditions apply unless otherwise specified: commercial: t a = 0 c to +70 c, v cc = 5.0v 5%; military: t a = C55 c to +125 c, v cc = 5.0v 10% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level (4) guaranteed logic high normal inputs 2.0 v hysteresis inputs 3.0 v il input low level (4) guaranteed logic low 0.8 v i ih input high current v cc = max., v in = v cc 5.0 m a i il input low current v cc = max., v in = gnd C5.0 m a i oz off state (hi-z) v cc = max. v o = 0v C10 m a v o = 3v 10 i os short circuit current v cc = max. (3) C20 C150 ma v oh output high voltage v cc = min. i oh = C6ma coml. 2.4 v v in = v ih or v il i oh = C4ma mil. 2.4 v ol output low voltage v cc = min. i ol = 12ma coml. 0.5 v v in = v ih or v il i ol = 6ma mil. 0.5 v h hysteresis clear , mle, ple , sle, synclk , sclken 200 mv notes: 2552 tbl 21 1. for conditions shown as min. or max., use appropriate value specified above for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient temperature and maximum loading. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. these input levels provide zero noise immunity and should only be static tested in a noise-free environment.
11.7 21 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges dc electrical characteristics over operating range (con?.) the following conditions apply unless otherwise specified: commercial: t a = 0 c to +70 c, v cc = 5.0v 5%; military: t a = C55 c to +125 c, v cc = 5.0v 10% symbol parameter test conditions (1) min. typ. (2) max. unit i ccq quiescent power supply current v in = v cc or gnd 5 ma cmos input levels v cc = max. all inputs outputs disabled i ccqt quiescent power supply current v ih = 3.4v, v il = 0v 1 ma/ ttl input levels v cc = max. all inputs input outputs disabled i ccd1 dynamic power supply current f cp = 10mhz, 50% duty cycle com'l. 100 ma f = 10mhz v ih = v cc , v il = gnd read mode, outputs disabled mil. 115 i ccd2 dynamic power supply current f cp = 20mhz, 50% duty cycle com'l. 200 ma f = 20mhz v ih = v cc , v il = gnd read mode, outputs disabled mil. 230 notes: 2552 tbl 22 1. for conditions shown as min. or max., use appropriate value specified above for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient temperature, and maximum loading. 3. total supply current is the sum of the quiescent current and the dynamic current and is calculated as follows: i cc = i ccq + i ccqt (n t x d t ) + i ccd (f op ) where: n t = total # of quiescent ttl inputs d t = ac duty cycle C % of time high (ttl) f op = operating frequency
11.7 22 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac parameters - 49c465a propagation delay times 32-bit 64-bit 64-bit system system ?enerate standalone only lower upper slice slice slice slice code id=00 code id=01 code id=10 code id=11 parameter description com. mil. com. mil. com. mil. com. mil. refer to number parameter from to timing diagram name input (edge) output (edge) max. max. max. max. max. max. max. max. unit figure generate (write) parameters 01 t bc be n cbo 15 20 15 20 15 20 ns 02 t bm be n md out 15 20 15 20 15 20 ns 03 t mc md in cbo 15 18 ns 10 04 t pcc pc bi cbo 12 18 ns 7 05 t ppe p xin perr 12 18 12 18 12 18 ns 06 t sc cbo 14 18 14 18 14 18 14 18 ns 7 07 t sm sd in md out 12 18 12 18 12 18 ns 7 08 t spe perr 12 18 12 18 12 18 ns detect (read) parameters 09 t ce err err low 14 18 12 18 ns 8,10 10 t cme cbi merr = low 15 20 15 20 ns 8,10 11 t csy syo 12 18 12 18 ns 8,10 12 t me err err 12 18 12 18 ns 8,10 13 t mme md in merr 16 20 16 20 ns 8,10 14 t msy syo 16 20 12 18 12 18 ns 8,10 correct (read) parameters 15 t cs cbi sd out 16 20 16 20 ns 8,11 16 t mp px 18 22 18 22 18 22 ns 8,11 17 t ms md in sd out 14 18 ns 8,11 18 t msy syo 16 20 12 18 1 218 ns 8,11 19 t pcs pcbi sd out 13 18 ns 11 diagnostic parameters 20 t clr clear = low sd out 15 20 15 20 15 20 ns 15 21 t mis mode id sd out 15 20 15 20 15 20 ns 15 notes: 1. where edge is not specified, both high and low edges are implied. 2. bold indicates critical system parameters. 2552 tbl 24
11.7 23 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges propagation delay times from latch enables parameter description com.?. mil. refer to parameter from to timing diagram number name input (edge) output (edge) max. max. unit figure 22 t mlc cbo * 16 20 ns 13 23 t mle err * 13 18 ns 8, 10, 11 24 t mlme mle = high merr *16 20 ns 8 25 t mlp px * 18 22 ns 8, 11 26 t mls sd out * 18 22 ns 8, 10, 11 27 t mlsy syo * 15 20 ns 8, 10 28 t pls ple = low sd out * 10 12 ns 8, 11 29 t plp ple = low px * 13 18 ns 8, 11 30 t slc sle = high cbo * 16 20 ns 7, 9 31 t slm sle = high md out * 12 18 ns 7, 9 note: 2552 tbl 27 * = both high and low edges are implied. ac parameters - 49c465a enable and disable times parameter description com?. mil. refer to parameter from to timing diagram number name input (edge) output (edge) min. max. min. max. unit figure 32 t beszx ben = high sd out * 2 13 2 16 ns 8, 10, 11 33 t besxz low hi C z 2 11 2 14 ns 34 t bepzx ben = high p out * 2 13 2 16 ns 8, 11 35 t bepxz low hi C z 2 11 2 14 ns 36 t ceczx cboe = low cbo * 2 13 2 16 ns 7, 9 37 t cecxz high hi C z 2 11 2 14 ns 38 t memzx moe = low md out * 2 13 2 16 ns 7, 9 39 t memxz high hi C z 2 11 2 14 ns 8, 10 40 t seszx soe = low sd out * 2 13 2 16 ns 8, 10 41 t sesxz high hi C z 2 11 2 14 ns 7, 9 note: 2552 tbl 28 * = delay to both edges.
11.7 24 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges minimum pulse width refer to parameter minimum pulse width com?. mil. timing diagram number name input conditions min. min. unit figure 59 t clear min. clear low time to clear diag. registers data = valid 8 10 ns 14 60 t mle min. mle high time to strobe new data md, cbi = valid 5 6 ns 61 t ple min. ple low time to strobe new data sd = valid 5 6 ns 62 t sle min. sle high time to strobe new data sd = valid 5 6 ns 63 t synclk min. synclk high time to clock in new data scken = low 5 6 ns 14 2552 tbl 33 set-up and hold times - 49c465a parameter description com.?. mil. refer to parameter from to timing diagram number name input (edge) output (edge) min. min. unit figure 42 t ssls sdin set-up * before sle = low 3 4 ns 7, 9 43 t sslh sdin hold * after sle = low 3 4 ns 7, 9 44 t mmls mdin set-up * before mle =low 3 4 ns 8, 10, 11 45 t mmlh mdin hold * after mle = low 3 4 ns 8, 10, 11 46 t cmls cbi set-up * before mle = low 3 4 ns 8, 10, 11 47 t cmlh cbi hold * after mle = low 3 4 ns 8, 10, 11 48 t mpls mdin set-up * before ple = high 10 12 ns 49 t mplh mdin hold * after ple = high 0 0 ns 50 t cpls cbi set-up * before ple =high 10 12 ns 51 t cplh cbi hold * after ple = high 0 0 ns 52 t pcpls pcbi set-up * before ple = high 10 12 ns 53 t pcplh pcbi hold * after ple = high 0 0 ns diagnostic set-up and hold times 54 t cscs cbi set-up * 10 12 ns 15 55 t mscs mdin set-up * before synclk=high 10 12 ns 15 56 t mlscs mle set-up =high 10 12 ns 15 57 t sescs sclken set-up =low 3 4 ns 15 58 t sesch sclken hold =low after synclk =high 3 4 ns 15 note: 2552 tbl 32 * = where edge is not specified, both high and low edges are implied. input pulse levels gnd to 3.0v input rise/fall times 1v/ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 18 2552 tbl 34
11.7 25 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac parameters - 49c465 propagation delay times 32-bit 64-bit 64-bit system system ?enerate standalone only lower upper slice slice slice slice code id=00 code id=01 code id=10 code id=11 parameter description com. mil. com. mil. com. mil. com. mil. refer to number parameter from to timing diagram name input (edge) output (edge) max. max. max. max. max. max. max. max. unit figure generate (write) parameters 01 t bc be n cbo 20 25 20 25 20 25 ns 02 t bm be n md out 20 25 20 25 20 25 ns 03 t mc md in cbo 17 20 ns 10 04 t pcc pc bi cbo 15 20 ns 7 05 t ppe p xin perr 15 20 15 20 15 20 ns 06 t sc cbo 16 20 16 20 16 20 16 20 ns 7 07 t sm sd in md out 15 20 15 20 15 20 ns 7 08 t spe perr 15 20 15 20 15 20 ns detect (read) parameters 09 t ce err err = low 16 20 15 20 ns 8,10 10 t cme cbi merr = low 20 24 20 24 ns 8,10 11 t csy syo 15 20 12 18 ns 8,10 12 t me err err = low 15 20 15 20 ns 8,10 13 t mme md in merr = low 20 24 20 24 ns 8,10 14 t msy syo 18 22 15 20 15 20 ns 8,10 correct (read) parameters 15 t cs cbi sd out 20 24 20 24 ns 8,11 16 t mp px 20 26 20 26 20 26 ns 8,11 17 t ms md in sd out 16 20 ns 8,11 18 t msy syo 18 22 15 20 15 20 ns 8,11 19 t pcs pcbi sd out 15 20 ns 11 diagnostic parameters 20 t clr clear = low sd out 20 24 20 24 20 24 ns 15 21 t mis mode id sd out 20 24 20 24 20 24 ns 15 notes: 1. where edge is not specified, both high and low edges are implied. 2. bold indicates critical system parameters. 2552 tbl 23
11.7 26 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges enable and disable times parameter description com?. mil. refer to parameter from to timing diagram number name input (edge) output (edge) min. max. min. max. unit figure 32 t beszx ben = high sd out * 2 15 2 18 ns 8, 10, 11 33 t besxz low hi C z 2 13 2 16 ns 34 t bepzx ben = high p out * 2 15 2 18 ns 8, 11 35 t bepxz low hi C z 2 13 2 16 ns 36 t ceczx cboe = low cbo * 2 15 2 18 ns 7, 9 37 t cecxz high hi C z 2 13 2 16 ns 38 t memzx moe = low md out * 2 15 2 18 ns 7, 9 39 t memxz high hi C z 2 13 2 16 ns 8, 10 40 t seszx soe = low sd out * 2 15 2 18 ns 8, 10 41 t sesxz high hi C z 2 13 2 16 ns 7, 9 note: 2552 tbl 26 * = delay to both edges. propagation delay times from latch enables parameter description com.?. mil. refer to parameter from to timing diagram number name input (edge) output (edge) max. max. unit figure 22 t mlc cbo * 20 24 ns 13 23 t mle err * 15 20 ns 8, 10, 11 24 t mlme mle = high merr *20 24 ns 8 25 t mlp px * 20 25 ns 8, 11 26 t mls sd out * 20 25 ns 8, 10, 11 27 t mlsy syo * 18 22 ns 8, 10 28 t pls ple = low sd out * 12 16 ns 8, 11 29 t plp ple = low px * 16 20 ns 8, 11 30 t slc sle = high cbo * 20 24 ns 7, 9 31 t slm sle = high md out * 15 20 ns 7, 9 note: 2552 tbl 25 * = both high and low edges are implied. ac parameters - 49c465
11.7 27 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges minimum pulse width refer to parameter minimum pulse width com?. mil. timing diagram number name input conditions min. min. unit figure 59 t clear min. clear low time to clear diag. registers data = valid 8 10 ns 14 60 t mle min. mle high time to strobe new data md, cbi = valid 5 6 ns 61 t ple min. ple low time to strobe new data sd = valid 5 6 ns 62 t sle min. sle high time to strobe new data sd = valid 5 6 ns 63 t synclk min. synclk high time to clock in new data sclken = low 5 6 ns 14 2552 tbl 30 set-up and hold times - 49c465 parameter description com.?. mil. refer to parameter from to timing diagram number name input (edge) output (edge) min. min. unit figure 42 t ssls sdin set-up * before sle =low 4 5 ns 7, 9 43 t sslh sdin hold * after sle = low 4 5 ns 7, 9 44 t mmls mdin set-up * before mle =low 4 5 ns 8, 10, 11 45 t mmlh mdin hold * after mle = low 4 5 ns 8, 10, 11 46 t cmls cbi set-up * before mle =low 4 5 ns 8, 10, 11 47 t cmlh cbi hold * after mle = low 4 5 ns 8, 10, 11 48 t mpls mdin set-up * before ple =high 12 15 ns 49 t mplh mdin hold * after ple = high 0 0 ns 50 t cpls cbi set-up * before ple =high 12 15 ns 51 t cplh cbi hold * after ple = high 0 0 ns 52 t pcpls pcbi set-up * before ple =high 12 15 ns 53 t pcplh pcbi hold * after ple = high 0 0 ns diagnostic set-up and hold times 54 t cscs cbi set-up * 12 15 ns 15 55 t mscs mdin set-up * before synclk=high 12 15 ns 15 56 t mlscs mle set-up = high 12 15 ns 15 57 t sescs sclken set-up = low 4 5 ns 15 58 t sesch sclken hold = low after synclk =high 4 5 ns 15 note: 2552 tbl 29 * = where edge is not specified, both high and low edges are implied. input pulse levels gnd to 3.0v input rise/fall times 1v/ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 18 2552 tbl 31
11.7 28 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac timing diagrams ?32-bit configuration note: 2552 drw 19 1. assumes that system data is valid at least 3ns (com.) before sle goes high. figure 7. 32-bit generate timing be n t besxz t besxz t sesxz t sesxz t ssls t sslh t spe t ppe t sm t slm t sc t slc t ceczx t besxz min. t besxz max. t sesxz min. t sesxz max. t ssls t sslh t spe t ppe t sm t slm t memzx t sc t slc t ceczx soe sle sd 0C31 p n perr moe md 0C31 cboe cbo t memzx be n = low to sdout disabled be n = low to sdout disabled soe = low to sd out disabled soe = low to sd out disabled sd in set-up to sle in = low sd in hold to sle in = low sd in to perr out p x to perr out sd in to mdout sle = high to md out moe = low to md out enabled sd in to cbo sle = high to cbo cboe = low to cbo enable max. min. max. min. max. min. min. max. max. max. max. max. max. max. parameter name propagation delay from to min./ max. (output) data in (input) m data out = s data in to 1 2 3 4 5 to 1 2 3 4 5 (1) (1) (1) (1)
11.7 29 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac timing diagrams ?32-bit configuration note: 2552 drw 20 1. assumes that memory data and checkbits are valid at least 3ns (com.)/4ns (mil,) before mle goes high. figure 8. 32-bit detect timing t cmlh mle md 0C31 moe min. parameter name propagation delay from to min./ max. (output) valid data in cbi valid checkbits in t cmls t mmlh t mmls t memxz t msy t csy t mlsy t me t ce t mlex t mme t cme t mlmex syo err merr t cmlh t cmls t mmlh t mmls t memxz t msy t csy t mlsy t me t ce t mlex t mme t cme t mlemx checkbit hold to mle = low checkbit set-up to mle = low md in hold to mle = low md in set-up to mle = low moe = high to md out disabled md in to syo out checkbits in to syo out mle = high to syo out md in to err = low checkbits in to err = low mle = high to err = low md in to merr = low checkbits in to merr = low mle = high to merr = low min. min. min. max. max. max. max. max. max. max. max. max. max. to 1 2 3 4 5 to 1 2 3 4 5 (1) (1) (1) (1) (1) (1) (1) (1)
11.7 30 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac timing diagrams ?32-bit configuration note: 2552 drw 21 1. assumes that memory data and checkbits are valid at least 3ns (com.)/4ns (mil.) before mle goes high. figure 9. 32-bit correct timing t cmlh mle md 0C31 moe min. parameter name propagation delay from to min./ max. (output) cbi valid checkbits in t cmls t mmlh t mmls t memxz t mls t cmlh t cmls t mmlh t mmls t memxz checkbit hold to mle = low checkbit set-up to mle = low md in hold to mle = low md in set-up to mle = low moe = high to md out disabled min. min. min. max. t pls t beszx t seszx t cs t ms t mp t mlp t plp t bepzx t sep corrected data out parity out t mls t pls t beszx t seszx t cs t ms t mp t mlp t plp t bepzx t sep mle in = high to sd out ple = low to sd out be n = high to sd out enabled soe = low to sd out enabled cbi to corrected sd out md in to corrected sd out md in to parity out mle = high to parity out ple = low to parity out be n = high to parity out soe = low to parity out max. max. max. max. max. max. max. max. max. max. max. ple be n soe p 0C3 to 1 2 3 4 5 to 1 2 3 4 5 (1) (1) (1) (1) (1) (1) valid data in
11.7 31 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac timing diagrams ?64-bit configuration note: 2552 drw 22 1. assumes that system data is valid at least 3ns (com.)/4ns (mil.) before sle goes high. figure 10. 64-bit generate timing ?(64-bit cascading system) be n t sesxz t sesxz t ssls t sslh t ppe t sm t sc t slc t ceczx t sesxz min. t sesxz max. t ssls t sslh t ppe t sm t memzx t sc t slc t ceczx soe sle sd (l & u) p x perr moe md (l & u) cboe cbo t memzx soe = high to sd out disabled soe = high to sd out disabled sd in set-up to sle in = low sd in hold to sle in = low px to perr sd in to md out moe = low to md out enabled sd lower in to cbo sle in = high to cbo cboe = low to cbo enabled min. max. min. min. max. max. max. max. max. parameter name propagation delay from to min./ max. (output) data in (input) md data out = sd data in lower 465 partial checkbits out partial checkbits in upper 465 final checkbits out t pcc t pcc pcbi to cbo max. 3 inter-chip delay (design dependent) pcbi cbo parity in t slm t slm sle = high to md out max. t bem t bem be n to md out max. max. both 465s to 1 2 3 4 5 to 1 2 3 4 5 (1) (1) (1) (1) (1)
11.7 32 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac timing diagrams ?64-bit configuration note: 2552 drw 23 1. assumes that system data is valid at least 3ns (com.)/4ns (mil.) before sle goes high. figure 11. 64-bit detect timing t cmlh mle md (l) moe min. parameter name propagation delay from to min./ max. (output) cbi valid checkbits in t cmls t mmlh t mmls t memxz t mls t cmlh t cmls t mmlh t mmls t memxz cbi hold to mle = low cbi set-up to mle = low md in hold to mle = low md in set-up to mle = low moe = high to md out disabled min. min. min. max. t beszx t seszx corrected data out partial syndrome out t mls t beszx t seszx mle = high to sd out be n = high to sd out enabled soe = low to sd out enabled max. max. max. be n soe sd 0C31 syo md (u) (output) t msy t csy t mlsy t cme t mlme t ce t mle t mme t me 3 lower 465 upper 465 partial syndrome in t msy t csy t mlsy t cme t mlme t ce t mle t mme t me md lower in to syo out cbi to syo mle = high to syo cbi to merr mle = high to merr cbi to err mle = high to err md in to merr md in to err inter-chip delay (design dependent) max. max. max. max. max. max. max. max. max. cbi merr err both 465s to 1 2 3 4 5 to 1 2 3 4 5 (1) (1) (1) (1) (1) (1) (1) valid data in valid data in
11.7 33 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac timing diagrams ?64-bit configuration figure 12. 64-bit correct timing (lower slice) note: 2552 drw 24 1. assumes that memory data and checkbits are valid at least 4ns (com.) before mle goes high. t cmlh mle md 0C31 moe min. parameter name propagation delay from to min./ max. (output) cbi valid checkbits in t cmls t mmlh t mmls t memxz t mls t cmlh t cmls t mmlh t mmls t memxz cbi hold to mle = low cbi set-up to mle = low md in hold to mle = low md in set-up to mle = low moe = high to md out disabled min. min. min. max. t pls t beszx t seszx t cs t ms t csy t mlp t plp t bepzx t sep corrected data out parity out t mls t pls t beszx t seszx t cs t ms t csy t mlp t plp t bepzx t sep mle in = high to sd out ple = low to sd out be n = high to sd out enabled soe = low to sd out enabled cbi to corrected sd out md in to corrected sd out cbi to syndrome mle = high to parity out ple = low to parity out be n = high to parity out soe = low to parity out max. max. max. max. max. max. max. max. max. max. max. ple be n soe sd 0C31 p 0C3 partial checkbits in from upper pcbi t csy t csy cbi to syndrome max. t msy t msy md in to syndrome max. t mp t mp md in to parity out max. partial syndrome out syo 64-bit u/l slice to 1 2 3 4 5 to 1 2 3 4 5 (1) (1) (1) (1) (1) (1) valid data in
11.7 34 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac timing diagrams ?64-bit configuration note: 2552 drw 25 1. assumes that memory data and checkbits are valid at least 4ns (com.) before mle goes high. figure 13. 64-bit correct timing (upper slice) t cmlh mle md 0C31 moe min. parameter name propagation delay from to min./ max. (output) cbi valid checkbits in t cmls t mmlh t mmls t memxz t mls t cmlh t cmls t mmlh t mmls t memxz cbi hold to mle = low cbi set-up to mle = low md in hold to mle = low md in set-up to mle = low moe = high to md out disabled min. min. min. max. t pls t beszx t seszx t cs t msy t mlp t plp t bepzx t sep corrected data out parity out t mls t pls t beszx t seszx t cs t msy t mlp t plp t bepzx t sep mle in = high to sd out ple = low to sd out be n = high to sd out enabled soe = low to sd out enabled cbi to corrected sd out md in to corrected sd out mle = high to parity out ple = low to parity out be n = high to parity out soe = low to parity out max. max. max. max. max. max. max. max. max. max. ple be n soe sd 0C31 p 0C3 t mp t mp md in to parity out max. partial checkbits/ syndrome out syo t ms t ms md in to corrected sd out max. 64-bit u/l slice to 1 2 3 4 5 to 1 2 3 4 5 (1) (1) (1) (1) (1) (1) valid data in
11.7 35 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac timing diagrams ?64-bit configuration note: 2552 drw 26 1. assumes that system data is valid at least 3ns (com.) before sle goes high. 2. assumes that memory data is valid at least 4ns (com.) before mle goes high. figure 14. 64-bit single chip "generate only" timing t slc moe sd bus soe max. parameter name propagation delay from to min./ max. sle t sslh t ssls t slc t sslh t ssls sle = high to cbo sd in hold to sle in = low sd in set-up to sle in = low min. min. t mmlh t mlc t ceczx final checkbits out t mmlh t mlc t ceczx md in hold to mle in = low mle in = high to cbo cboe = low to cbo enabled min. max. max. md bus mle cboe cbo (soe = tied high) single 465 t mc t mc bits 0C31 to cbo max. t sc t sc bits 32C63 to cbo max. t mmls t mmls md in set-up to mle in = low min. (moe = tied high) to 1 2 3 4 5 to 1 2 3 4 5 (1) (2) (2) (2) (1) (1) valid data in valid data in
11.7 36 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges ac timing diagrams ?diagnostic timing 2552 drw 27 figure 15. 32-bit diagnostic timing cbi parameter name propagation delay from to min./ max. t cscs checkbits in 465 md bus mle sclken memory datain valid dataout t mscs t mlscs t sescs t sesch t synclk t scs t clear t clr t cscs t mscs t mlscs t sescs t sesch t synclk t scs t clear t clr cbi set-up to synclk = high mdin set-up to synclk = high mle = high set-up to synclk = high sclken set-up to synclk = high sclken = hold after synclk = high sclken pulse width sclken = high to sd out clear pulse width clear = low to sd out min. min. min. min. min. max. min. max. synclk clear sd bus to 1 2 3 4 5 to 1 2 3 4 5
11.7 37 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges switch position test circuits and waveforms test circuits for all outputs set-up, hold and release times pulse width propagation delay enable and disable times pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. test switch disable low enable low closed all other tests open open drain definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. 2552 drw 30 2552 drw 31 2552 drw 32 2552 drw 33 notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns 2552 drw 34 2552 tbl 35
11.7 38 idt49c465/a 32-bit flow-thru error detection and correction unit military and commercial temperature ranges idt 49c465 device type xx package x process/ temperature range blank b pqf g commercial (0 c to +70 c) military (C55 c to +125 c) plastic quad flatpack pin grid array 49c465 32-bit flow-thru ? edc 2552 drw 35 xx speed blank a standard speed high speed ordering information

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